The disclosed invention relates generally to the digital measurement of an unknown input voltage and more particularly to an analog to digital converter employing a modified version of dual slope integration. As illustrated in FIG. 1, in dual slope integration a test voltage V.sub.t is applied to the input of an integrator for a run-up (RU) interval of duration T. A reference discharging voltage V.sub.d is then applied to the integrator input during a run-down (RD) interval ending when the integrator is totally discharged. The duration t of the RD interval is measured and the value of V.sub.t is calculated as tV.sub.d /T.
The value of t is typically measured by counting the number of clock pulses contained in the RD interval. For a given clock rate the sensitivity of the A/D converter increases with an increase in t. Therefore, sensitivity can be increased by decreasing V.sub.d. However, an instrument user typically needs or wants a short measurement time so that large values of t are impractical. In the prior art method illustrated in FIG. 2 an increase in sensitivity is achieved without requiring a long RD interval by first using a large discharging voltage V.sub.dl to discharge the integrator to a preselected level V.sub.1 and then using a much smaller discharging voltage V.sub.d2 to totally discharge the integrator. The time t.sub.1 that V.sub.d1 is applied and the time t.sub.2 that V.sub.d2 is applied are measured for use in calculating V.sub.t.
The sensitivity can also be increased by increasing the maximum value V.sub.m of the output voltage. For a fixed duration of the RU interval (typically 1/60 second to discriminate against the 60 Hertz background Interference) this is achieved by reducing the value of the input resistance R.sub.i of the integrator to increase the slope of the integrator output voltage during run-up. However, for an op Amp integrator the integrator output voltage must be less then the op Amp power supplies. As illustrated in FIG. 2, a large slope during the RU interval can be empoyed without exceeding the voltage of the power supplies by utilizing a saw-tooth shaped curve during the RU interval. In this approach whenever the integrator output voltage is detected as exceeding a voltage V.sub.2 a discharging voltage V.sub.d3 is applied along with the test voltage V.sub.t to the integrator input for an interval of duration t.sub.3. The integrator output voltage therefore has a slope proportional to V.sub.t +V.sub.d3 during such intervals. The total time t.sub.4 equal to the sum of the intervals of duration t.sub.3 during which V.sub.d3 is applied is measured for use in calculating V.sub.t. In the example shown in FIG. 2A the value of V.sub.t is calculated as (t.sub.1 V.sub.d1 +t.sub.2 V.sub.d2 +t.sub.4 V.sub.d3) /T.
Unfortunately the implementation of the method illustrated in FIG. 2 requires 4 extra comparators and 4 extra voltage sources to detect crossings by the integrator output voltage of the comparator voltage levels at V.sub.1, -V.sub.1, V.sub.2, and -V.sub.2 volts. These additional comparators and voltage sources increase the complexity and expense of such an A/D converter. In addition the saw-tooth method maintains the integrator output voltage near V.sub.2 for much of the run-up interval so that dielectric absorption of the integrator capacitor can introduce a significant error. Another source of error is the hysteresis of the comparator used to detect the zero voltage level crossing at the end of the run-down interval. The effect of this hysteresis is that the comparator detects a "zero" crossing at a slightly different voltage for a negative sloping integrator output voltage than for a positive sloping integrator output voltage.
The conversion technique illustrated in FIG. 2A also produces a multiplicative error due to switch time mismatch errors. In FIG. 2B is shown the switching characteristics for a typical switch such as the switch which is used to selectively couple V.sub.d3 into the circuit. The ideal switching curve for a switch turned on at time t.sub.1 and turned off at time t.sub.2 is indicated by the dotted curve in FIG. 2B. The solid curve shows the actual switch response. Because the turning-on and turning-off characteristics are typically not symmetric the total ideal charge transfer proportional to V.sub.d3 (t.sub.2 -t.sub.1) will not equal the actual charge transfer. Because of the switching time mismatch the switch is effectively held open for an additional switching mismatch time .DELTA.t can be positive or negative) thereby transferring a charge proportional to V.sub.d3 (t.sub.2 -t.sub.1 +.DELTA.t). In a switching scheme such as that in the prior art scheme of FIG. 2 in which the number n of switch activations is proportional to the magnitude of the test signal, such mismatch of switching times will produce an error in the A/D conversion proportional to n.DELTA.t. The integer n is an integer valued step function increasing with increase in the magnitude of the test signal and representing a coarse valuation of V.sub.t. The switching time mismatch error results in a multiplicative error in this coarse valuation of V.sub.t. To correct for this error such an A/D converter requires a scaling factor which adjusts the measured result before output of the digital result. Such adjustment requires the measurement of a known reference voltage to set the scaling factor and then each subsequent measurement requires a multiplication of the coarse valuation by this factor. Since subtractions are more easily and rapidly executed than multiplications it would be advantageous to convert switch time mismatch scaling errors into offset errors which can be eliminated by subtraction.